1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor optical modulator capable of performing high-speed modulation by using an electrical signal, an optical semiconductor device usable as a semiconductor laser device, and a method of fabricating the same.
2. Description of the Related Art
Recently, research and development are being actively done to increase the capacity of a trunk optical communication system. In a direct modulation system in which a semiconductor laser serves as both an oscillator and a modulator, the light source can be constituted by a single element. Accordingly, it is possible to simplify the system and decrease the system cost. To obtain a high-speed modulating operation in a semiconductor laser, the relaxation oscillation frequency must be high. For this purpose, it is crucial to decrease the threshold value and increase the output and accordingly it is essential to reduce the leakage current, in addition to improving the laser medium itself, e.g., forming an active layer from a multiple quantum well structure. Furthermore, in a semiconductor laser which directly modulates light intensity by using an injected current, a small element parasitic capacitance also is required.
On the other hand, in an external modulator system by which long-distance optical transmission is possible because wavelength chirping is little, a field absorption type semiconductor optical modulator capable of being monolithically integrated with a semiconductor laser, as a light source, is being vigorously developed. The light absorption coefficient of this field absorption type semiconductor optical modulator is controlled by externally applying a voltage signal. To obtain a high extinction ratio, it is necessary to evenly apply an electric field to a light absorbing layer. Furthermore, to achieve large-capacity optical transmission, the element parasitic capacitance must be small enough to allow a high-speed modulating operation.
In an optical semiconductor device with a conventional semiconductor buried structure used as a semiconductor laser and an optical modulator, the parasitic capacitance of an element formed by evenly burying it in a semiconductor substrate is reduced by processing vicinities around an optical waveguide stripe of the element into a narrow mesa shape. FIG. 1 is a sectional view in a plane perpendicular to the direction of wave propagation of an optical semiconductor device with a conventional semiconductor buried structure. In FIG. 1, reference numeral 101 denotes an n-type InP substrate; 102, an optical waveguide layer; 103, an Fe-doped semi-insulating InP buried layer; 104, a p-type InP cladding layer; 105, a p-type InGaAs contact layer; 106, an SiO.sub.2 film; 107, a p-type Au/Zn/Au ohmic electrode; 108, a Ti/Pt/Au interconnecting line; 109, a Ti/Pt/Au bonding pad; and 110, an n-type AuGe/Ni/Au ohmic electrode.
This semiconductor device is fabricated as follows. A mesa stripe 111 including an active layer 102 is formed on an n-type InP substrate 101, and the two side surfaces of the mesa stripe 111 are buried with an Fe-doped semi-insulating InP layer 103. A p-type InP cladding layer 104 and a p-type InGaAs contact layer 105 are formed in this order on the mesa stripe region 111 and the Fe-doped semi-insulating InP layer 103. Thereafter, isolation trenches 113 are formed in regions on the two sides of the mesa stripe 111 by wet etching using a Br-based etchant.
In the optical semiconductor device with the structure illustrated in FIG. 1, to reduce the element parasitic capacitance it is necessary to process vicinities around the mesa stripe 111 into a narrow mesa shape and decrease the width of a mesa stripe 112 sandwiched between the isolation trenches 113. Unfortunately, since side etching necessarily occurs in the wet-etching process using a Br-based etchant, it is difficult to form the mesa stripe 112 with a controlled small width. Additionally, the flatness of the structure after the narrow mesa processing is low. This makes it difficult to form an electrode on the structure.
FIG. 2 shows a method by which the narrow mesa processing for an element is done by forming isolation trenches 113 by dry etching which causes no side etching. In this method the width of a mesa stripe 112 is readily controlled. However, the side surfaces of the isolation trenches 113 are nearly perpendicular to the substrate surface. Consequently, an electrode formation step is extremely difficult to perform after the narrow mesa processing. Even if the electrode formation is done, an interconnecting or wiring line 108 easily breaks particularly on the side surfaces of the isolation trenches 113. This results in the difficulty in step interconnection for connecting a p-type ohmic electrode 107 formed on the mesa stripe 112 and a bonding pad 109 formed outside the isolation trench 113.